1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of producing the semiconductor device, and particularly, to a semiconductor device having a high operating speed due to stress application, and a method of producing the semiconductor device.
2. Description of the Related Art
A semiconductor device is made at a smaller and smaller scale in order to increase its operating speed and expand its functions, and so far, large scale integrated circuits (LSI) including transistors having a gate length less than 100 nm have been fabricated. When a transistor is miniaturized following a scaling rule more and more, the operating speed of the semiconductor device increases accordingly. However, when the gate length becomes extremely short, a threshold voltage decreases, namely, a so-called “short channel” effect occurs. Various methods are proposed to reduce the short channel effect, but effects of these methods are becoming more and more limited.
On the other hand, since mobility of holes is lower than mobility of electrons in silicon, it has been a crucial issue in the related art to increase the operating speed of a p-channel MOS (Metal-Oxide-Silicon) transistor, in which holes serve as carriers.
The p-channel MOS transistor is a component of a CMOS (Complementary MOS) inverter circuit, which is a basic element of a logic circuit. Hence, if the p-channel MOS transistor cannot operate at high speed, speed of the CMOS inverter circuit cannot be increased, either, and in turn, speed of the LSI cannot be increased.
A method is well know for improving hole mobility by applying a compressive stress to a channel region of a silicon substrate.
FIG. 1 is a cross-sectional view of a p-channel MOS transistor 100 involving compressive stress.
As shown in FIG. 1, a gate electrode 203 is arranged on a silicon substrate 201 with a gate insulating film 202 in between. On side walls of the gate electrode 203, side-wall insulating films 204A and 104B are provided to cover the surface of the silicon substrate 201.
In the silicon substrate 201, a channel region is formed beneath the gate electrode 103. In addition, in the silicon substrate 201, a source extension region 201A and a drain extension region 101B, in which p-type impurity elements are implanted, are formed on the two sides of the gate electrode 203. Further, a source region 201S and a drain region 201D, in which p-type impurity elements are implanted, are formed outside the source extension region 201A and the drain extension region 201B. Holes move from the source region 201S, and pass through the source extension region 201A, the channel region, and the drain extension region 201B, and finally arrive at the drain region 201D. Magnitude of a current of the holes is controlled by a gate voltage applied to the gate electrode 203 in the channel region.
Further, in the p-channel MOS transistor 200, SiGe mixed crystal layers 205A and 205B are formed in regions outside the side-wall insulating films 204A and 204B in the silicon substrate 201. The SiGe mixed crystal layers 205A and 205B are formed in the silicon substrate 201 by epitaxial growth. Because the lattice constant of the SiGe mixed crystal layers 205A and 205B is greater than the lattice constant of the silicon substrate 201, a compressive stress is induced in the SiGe mixed crystal layers 205A and 205B in a horizontal direction as indicated by arrows “a” in FIG. 1. Due to the compressive stress, lattices of the SiGe mixed crystal layers 205A and 205B stretch in a vertical direction as indicated by an arrow “b” in FIG. 1, namely, distortion of the lattices occurs.
Due to this distortion, in the channel region of the silicon substrate 201, which is sandwiched by the SiGe mixed crystal layers 205A and 205B, the lattice of the silicon substrate 201 stretches in the vertical direction as indicated by an arrow “c” in FIG. 1, in response to the stretch of the lattices of the SiGe mixed crystal layers 205A and 205B. As a result, in the channel region of the silicon substrate 201, a uniaxial compressive stress is induced in the horizontal direction as indicated by arrows “d” in FIG. 1.
In the p-channel MOS transistor 200 shown in FIG. 1, because of the uniaxial compressive stress in the channel region, symmetry of the silicon crystal in the channel region is locally modulated. In response to the change of the symmetry in the channel region, the degeneracy of heavy-hole valence bands and light-hole valence bands is removed. As a result, the hole mobility increases in the channel region, and the operating speed of a transistor rises. Particularly, the increase in hole mobility due to the compressive stress locally induced in the channel region and increase in transistor operating speed are significant in a transistor having a gate length less than 100 nm.
For example, reference can be made to U.S. Pat. No. 6,621,131 (below, referred to as “reference 1”) for details of the technique.